Wires

SymbolIdentification(new_symbol, old_symbol)

Class formally identifying two symbols as equal.

Warning

This class should not be instantiated directly. It is automatically created and accessed when required.

PARAMETER	DESCRIPTION
new_symbol	the new symbol TYPE: Symbol
old_symbol	the symbol to replace TYPE: Symbol

Source code in psymple/build/wires.py

def __init__(self, new_symbol: Symbol, old_symbol: Symbol):
    """
    Create a symbol identification.

    Args:
        new_symbol: the new symbol
        old_symbol: the symbol to replace
    """
    self.old_symbol = old_symbol
    self.new_symbol = new_symbol

VariableAggregationWiring(child_ports, parent_port, output_name)

Stores the connection of child variable ports in a composite ported object to a specified parent port or internal variable.

Warning

This class should not be instantiated on its own. Instead, use psymple.build.CompositePortedObject.add_variable_wire or psymple.build.CompositePortedObject.add_wires.

PARAMETER	DESCRIPTION
child_ports	list of ports whose variables will be aggregated. TYPE: list[str]
parent_port	variable port to expose the aggregation. TYPE: str
output_name	name to assign internally to the aggregation if it is not exposed. TYPE: str

Source code in psymple/build/wires.py

def __init__(self, child_ports: list[str], parent_port: str, output_name: str):
    """
    Create a variable wire.

    Args:
        child_ports: list of ports whose variables will be aggregated.
        parent_port: variable port to expose the aggregation.
        output_name: name to assign internally to the aggregation if it is
            not exposed.
    """
    self.child_ports = child_ports
    self.parent_port = parent_port
    self.output_name = output_name

DirectedWire(source_port, destination_ports)

Stores the connection of an input port or child output port in a composite ported object to a child input ports and/or an output port.

Warning

This class should not be instantiated on its own. Instead, use psymple.build.CompositePortedObject.add_directed_wire or psymple.build.CompositePortedObject.add_wires.

PARAMETER	DESCRIPTION
source_port	initial port which the wire reads from. TYPE: str
destination_ports	list of ports to which the read value is provided. TYPE: list[str]

Source code in psymple/build/wires.py

def __init__(self, source_port: str, destination_ports: list[str]):
    """
    Create a directed wire.

    Args:
        source_port: initial port which the wire reads from.
        destination_ports: list of ports to which the read value is provided.
    """
    self.source_port = source_port
    self.destination_ports = destination_ports